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The heart of analogue stage is Burr-Brown IC - PGA2310. It's able to controll the gain of two channels over a 127dB range in 0.5dB steps.

The main audio PCB contains source select relays, PGA2310 with opamp input output stage, balanced, USB, digital and line inputs, balanced and digital output and headphone amplifier.

Main analogue PCB:

7.1 channel, PGA2310 preamplifier 1

7.1 channel, PGA2310 preamplifier 2

Main signal path:

Here is schematic of main signal path. PGA2310 needs to be driven with low impedance so that input is buffered with OPA2134. There's sub and ultrasonic filter before input buffer to avoid DC problems and HF noise. The output opamp takes care of driving the next stage.

7.1 channel, PGA2310 preamplifier 3


  • Balanced input:

    Schematic of balanced input. Converts balanced signal to single ended that can PGA2310 handle with.

  • Digital input:

    Schematic of digital input. After converting to TTL level the digital stream goes to DIR1703 SPDIF receiver. Open BRSEL pin sets default sampling rate to 48kHz. SCK pins sets system clock to 384fS so that XTI pin gets 18.432MHz from master clock. UNLOCK bit signs if SPDIF signal is locked BRATE shows locked sampling frequency. Audio data format is set to 24bit IIS by FMT pins

    In PCM1793 IC the input audio data format is also set to 24bit I2S by FMT pins. Deemphasis (DEMP) is disabled.

    7.1 channel, PGA2310 preamplifier 4

  • USB input:

    USB input is nothing more but the standard producent application from PCM2702 datasheet. /PLYBCK pin is connected to the microcontroller to indicate if device is atached to the USB bus.


  • Balanced out:

    Schematic of balanced output. It is a simple balanced line driver on DRV134 IC.

  • Digital output:

    Schematic of digital output. After converting by OPA1632 signal goes to PCM1804. OPA2134 gives reference voltage for input stage. PCM1804 works in mater mode (S/M = LOW). Oversampling Ratio is set to single rate with 384fS system clock by OSR pins. Data format is 24bit I2S.

    Digital data goes to SPDIF tranciever DIT4096. This IC works in hardware, slave mode (MODE = HIGH, MS/NC = LOW). CLK bits set to 384fS and MLCK gets 18.432MHz form master clock. FMT are also set to 24bir I2S data format. CSS pin is set low to enable channel status pins. Channel status data are set to proffesional mode, digital audio data without pre-emphassis applied (L, COPY, AUDIO, EMPH pins). Next digital signal is converted to SDPIF standard hand-made digital transformer (2:1).

    DIT4096 digital transformer

  • Headphone amplifier:

    Schematic of headphone amplifier. Switch on the front panel below headphone plug disables all the outputs when needed.

Master clock:

Schematic of master clock. The heart of this part is PLL1700 IC with 27MHz crystal. MODE pin set hight sets the IC to work in hardware mode. FS pins are set to 48kHz FS. The outpin SCK03 gives requestes 18.432kHz clock to feed SPDIF receiver, transmitter and ADC IC.


On the next page surround stage...

Introduction | Main | Input | Output


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